1. Field of the Invention
The present invention relates to an insulated-gate semiconductor device, and particularly to an insulated-gate semiconductor device in which an operation region is sufficiently secured, and in which a high reverse breakdown voltage is maintained.
2. Description of the Related Art
In a conventional insulated-gate semiconductor device, a transistor cell is not disposed below a gate pad electrode. This technology is described, for instance, in Japanese Patent Application Publication No. 2002-368218 (FIG. 6 to FIG. 8).
Meanwhile, a protection diode is disposed below the gate pad electrode in some cases, and a number of pn junctions are connected to each other in series in the protection diode, for example. Moreover, a diffusion region of high-concentration impurities is sometimes formed in a substrate below the gate pad electrode in order to secure a reverse breakdown voltage between a drain and a source.
FIGS. 11A and 11B show one example of an n channel MOSFET as the conventional insulated-gate semiconductor device, in which a p+ type impurity region is formed below the gate pad electrode.
FIG. 11A is a plan view of the MOSFET. Note that, interlayer insulating films on the surface of the substrate are omitted in FIG. 11A. Metal electrode layers (a source electrode 47, a gate pad electrode 48, and a gate wiring 48a) are indicated by the dashed lines.
Gate electrodes 43 are formed into a stripe shape on the surface of a semiconductor substrate 31 with gate oxide films 41 interposed therebetween. The gate electrodes 43 are formed by patterning polysilicon which has been deposited and then doped with impurities to reduce the resistance. Source regions 45 are formed in the surface of the substrate 31 along the gate electrodes 43. The source regions 45 are formed along the gate electrodes 43, and have a stripe shape.
The source electrode 47 is formed on an operation region 51 where transistor cells are disposed. The gate pad electrode 48 is disposed on one edge of a chip. The gate wiring 48a, which is connected to the gate pad electrode 48, is formed around the chip.
FIG. 11B is a cross-sectional view taken along the line f-f in FIG. 11A.
The semiconductor substrate 31 provided with a drain region by stacking an n+ type silicon semiconductor substrate 31a with an n− type epitaxial layer 31b or the like. Multiple p type channel regions 34 are formed into a stripe shape in the surface of the semiconductor substrate 31. The multiple gate electrodes 43 are disposed into the stripe shape on the surface of the semiconductor substrate 31 on sides of the channel regions 34 while the gate insulating films 41 are interposed between the gate electrodes 43 and the semiconductor substrate 31. The n+ type source regions 45 are formed in the surface of the channel region 34 which is adjacent to the gate electrodes 43. The top of the gate electrode 43 is covered with the interlayer insulating film 46, and the source electrode 47 is formed thereon. The source electrode 47 is in contact with the source regions 45. The region surrounded by the gate electrodes 43 serves as the single transistor cell. A large number of these cells are disposed to form the operation region 51.
The gate pad electrode 48 is formed above the n− type semiconductor layer 31b outside the operation region 51. The gate pad electrode 48 is connected to the gate electrodes 43 in the operation region 51 through a gate leading electrode 43a. Moreover, a protection diode 43d formed by doping impurities in polysilicon is disposed below the gate pad electrode 48. The p+ type impurity region 49 is formed in the same pattern as that of the protection diode 43d. 
When the reverse voltage is applied between the source and the drain, depletion layers are spread from pn junctions between the channel regions 34 and the n− type semiconductor layers 31b over the operation region 51, thereby securing the reverse breakdown voltage between the source and the drain. Meanwhile, the protection diode 43d is formed on the one edge of the chip, the transistor cells (channel regions 34) are not disposed in the substrate surface below the protection diode 43d. For this reason, the p+ type impurity region 49 is formed in the substrate surface below the protection diode 43d. For example, if the pn junction is ended at the end portion of the operation region 51, the curvature of the depletion layer spreading at this region is increased, resulting in a problem that the reverse breakdown voltage between the source and the drain is deteriorated due to the electric field concentration. However, by forming the p+ type impurity region 49, the spreading of the depletion layer at the end portion of the operation region 51 can be moderately extended to the one edge of the chip. In other words, the curvature at the end of the operation region 51 is decreased, allowing the electric field concentration to be mitigated. Thus, it is possible to secure a predetermined reverse breakdown voltage between the source and the drain.
The protection diode 43d is made into a rectangular shape by patterning the polysilicon as shown in FIGS. 11A and B, for example. In the protection diode 43d, a number of pn junctions are formed in concentric circles as shown by the chain lines. Specifically, in the conventional art, the protection diode 43d having a large area is patterned below the entire lower surface of the gate pad electrode 48 so as to overlap the gate pad electrode 48. Accordingly, the p+ type impurity region 49 having the large area needs to be disposed from the outside of the operation region 51 where the transistor cells are not disposed to the one edge of the chip.
FIG. 12A and FIG. 12B are diagrams for describing the p+ type impurity region 49. FIG. 12A shows a perspective view of the p+ type impurity region 49 at the circle portion in FIG. 11A as viewed from the operation region 51 where the transistor cells (MOSFET) are disposed. FIG. 12B shows a plan view of another pattern of the p+ type impurity region 49, while omitting the interlayer insulating films on the surface, and indicating the metal electrode layers are indicated by the dashed lines.
The p+ type impurity region 49 is a diffusion region, and has the curvature of a spherical shape (FIG. 12A) at the end portion (the junction surface with the n− type epitaxial layer 31b) indicated by the circle in FIG. 11A. Here, suppose a case where a higher (for example, several hundreds V) reverse breakdown voltage is needed between the drain and the source in the pattern shown in FIG. 11. In this case, even if the p+ type impurity region 49 is disposed, high electric field is concentrated at the end portion (indicated by the arrows in FIG. 12A) having the curvature of the spherical shape. Accordingly, it is impossible to obtain a desired reverse breakdown voltage between the drain and the source.
Moreover, in order to reduce the on-resistance of the device, the specific resistance in the n− type epitaxial layer 31b needs to be reduced, for example. In such a case, the pattern of the p+ type impurity region 49 shown in FIG. 11 leads to decrease in the reverse breakdown voltage between the source and the drain.
In other words, when the property required for the operation region 51 is changed, the pattern of the p+ type impurity region 49 needs to be modified, besides the operation region 51, in order to obtain a predetermined reverse breakdown voltage between the source and the drain.
Specifically, by decreasing the curvature of the spherical shape, it is possible to secure a sufficient reverse breakdown voltage between the drain and the source. More specifically, as shown in FIG. 12B, by decreasing the curvature at corners of the p+ type impurity region 49 in the plane pattern, it is possible to decrease the curvature of the spherical shape shown in FIG. 12A, and accordingly to secure a predetermined reverse breakdown voltage.
Nevertheless, when the protection diode 43d is patterned below the gate pad electrode 48 so as to be substantially overlapped with the gate pad electrode 48, the p+ type impurity region 49 needs to be formed so as to cover the substrate surface below the protection diode 43d. In other words, since the p+ type impurity region 49 is formed in the same pattern as that of the protection diode 43d, the curvature at the corners thereof is caused to be small. Accordingly, in the pattern shown in FIG. 12, the transistor cells are hindered from being disposed adjacent to the gate pad electrode 48. It is inevitable not only to regulate or modify the design of the p+ type impurity region 49, but also to reduce the operation region (area for disposing the transistor cells).